The present invention relates generally to writing data to a banked memory array and more particular to a technique for banking multi-ported register file structures with a common write line.
Multi-ported register file memory arrays are typically large structures because each port requires its own set of word and bit lines. Moreover, each set of word lines requires its own decoder and driver, while each set of bit lines requires its own driver and/or sense amplifier. As the number of ports increase, these requirements become more burdensome.
This problem is further exaggerated when it is necessary to bank the register file memory array. Reading from the banked memory array does not pose a significant problem. A common read word line may connect to the banks of the memory array, and a column multiplexer on the bit lines. This configuration allows the common read word line to be asserted without causing a conflict. Writing to the banked memory array, however, poses more of a problem. A shared memory word line poses a problem in that data will be written into multiple banks, which cannot be allowed. This condition cannot be resolved with a column multiplexer either. One solution is to add a second set of write word lines to the array, such that there is a set in each bank. The area penalty associated with separate word lines for each bank is very severe because it increases the number of write lines and/or decoder and drivers in the array.
The present invention addresses the above-described limitation by providing a technique for writing in a banked, multi-ported register file memory array using common write word lines. This technique provides a more efficient way of writing data into a banked, multi-ported memory without increasing penalty due to area in the memory array.
According to another aspect of the present invention, a memory array is provided. The memory array comprises of a common write word line shared by a first memory bank and a second memory bank. The memory array also includes a first write buffer for buffering data to be written to the first memory bank. The memory array includes a second write buffer for buffering data to be written to the second memory bank. The memory array further comprises logic for receiving outputs from both of the first write buffer and second write buffer by writing data only into one of the first or second memory banks.
According to another aspect of the present invention, a memory array is provided. The memory array is comprised of a plurality of memory banks and a common write word line shared by the memory banks. The memory array includes a plurality of write buffers, wherein each write buffer is associated with one of the memory banks. The memory array further comprises a selector module for selecting a write buffer to write data into its associated memory bank. The memory array further includes a writing module within the write buffer for writing data into the selected memory bank by way of a signal to the memory bank.
According to another aspect of the present invention, in a banked memory array having a common write word line shared by the banks of the memory array and write buffers for each of the memory banks, a method for writing data into the banked memory array is provided. The method comprises the step of initializing the memory array to write data into one of a plurality of memory banks by activating the write word line. The method also comprises the step of selecting a write buffer to write data into a memory bank. The method further comprises the step of a writing module within the write buffer for writing data into the selected memory bank by way of a signal to the memory bank.
According to another aspect of the present invention, a memory array is provided. The memory array comprises common write word lines. The memory includes a plurality of memory banks for storing data. The memory array also includes a plurality of write buffers, wherein each of the write buffers are associated with one of the memory banks. The memory array also comprises selector logic for selecting memory banks to write data by way of a set of signals to the memory bank. The memory array further comprises distinguisher logic within the write buffers for sending a different set of signals to one of the memory banks that are not selected by the selector logic to retain data.